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Features
* * * * * * * * * * * *
Three Input Channels for 3D Antennas 2.8 mVPP Sensitivity Typically Ultra Low Current Operation Consumption 2 A Standby Current Typically 4 A Active Current Typically Power Supply 2V to 3.8V Carrier Frequency Range from 100 kHz to 150 kHz Wake-up Function for a Microcontroller Header Detection Baud Rate up to 4 kbps (ASK Modulation) Bi-directional Two-wire Interface ESD According to Automotive Requirements
Benefits
* Digital RSSI for Field Strength Measurement * Coils Input Range from 2.8 mVPP to 2.8VPP Typically * High Sensitivity
Ultra Low Power 125 kHz 3D Wake-up Receiver with RSSI ATA5282
Applications
* * * *
Passive Entry Go (PEG)/Car Access Position Indicator Home Access Control RFID Systems
1. Description
The ATA5282 is a 125-kHz ultra low power receiver IC with three input channels for Passive Entry Go applications. It includes all circuits for an LF wake-up channel. The three sensitive input stages of the IC amplifier demodulate and measure the input signal from the antenna coils. The microcontroller interface of the IC outputs the data signal as well as the measured RSSI values. During standby mode, the header detection unit monitors the incoming signal and generates a wake-up signal for the microcontroller if the IC receives a valid 125-kHz carrier signal. By combining the IC with an antenna coil, a microcontroller, an RF transmitter/transceiver and a battery, it is possible to design a complete hands-free key for Passive Entry Go applications.
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Figure 1-1.
Block Diagram
Battery
VDD
TC VSS
ATA5282
3 Channel Amplifier with AGC L1 Timing control
L2 Signal conditioner Header detection
NDATA/ NWAKEUP
L3
select 3 Vref 8 field strength Serial interface NSCL
2. Pin Configuration
Figure 2-1. Pinning TSSOP 8L
COIL1 COIL2 COIL3 VSS 1 2 3 4 8 7 6 5 VDD NDATA NSCL TC
Table 2-1.
Pin 1 2 3 4 5 6 7 8
Pin Description
Symbol COIL1 COIL2 COIL3 VSS TC NSCL NDATA VDD Function Input: Coil channel X Input: Coil channel Y Input: Coil channel Z Circuit ground Output: Current output for oscillator adjustment Input: Clock for serial interface (default high) Input/Output: I/O data for serial interface and field strength measurement/ Wake-up function (default high) Battery voltage
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3. Functional Description
The ATA5282 is a 3-channel ASK receiver for 125-kHz carrier signals. Its three active input stages with very low power consumption and high input sensitivity allow to connect up to 3 antennas for direction-independent wake-up function and data transfer. Without a carrier signal the ATA5282 operates in standby listen mode. In this mode, it monitors the 3 Coil inputs with a very low current consumption. To activate the IC and the connected control unit, the transmitting end must send a preamble carrier burst and the header code. When a preamble has been detected, the IC activates the internal oscillator and the header check. The last gap at the end of a valid header enables the NDATA output. During data transfer, the NDATA pin outputs the demodulated and merged signal of the 3 input stages. To achieve data rates up to 4 kbps for input signals from 2.8 mVPP to 2.8VPP it is necessary to control the gain of the amplifiers. Each of the 3 input stages contain an amplifier with Automatic Gain Control (AGC). It is used to adapt the gain to the incoming signal strength, and is also used as RSSI for field strength measurements. The integrated synchronous serial interface uses the NSCL together with the NDATA pin as clock and data line. It allows to control several functions as well as read out the received signal field strength. Enabling only single coil inputs, freezing the actual status of the automatic gain control or resetting the complete circuit to the initial state at any time are built-in features. When communication is finished or a time out event occurs, the internal watchdog timer or reset command via the serial interface sets the IC to standby listen mode.
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3.1
Functional State Diagram
This diagram gives an overview of the major tasks performed by the ATA5282. The detailed function of the automatic gain control that is active during preamble check, header check and data transfer is not shown here. Figure 3-1. ATA5282 State Diagram
Stand by
Waiting for RF-signal
Signal detected
Gap detected before 192 periods
Count 192 periods
Preamble check
No valid header within 2 ms
Gap detected after 192 periods 360 ms gone
No data received for 20 ms
Oscillator run
Start watchdog
Start header check
Start header timeout check
Check 8 edges of demodulated signal
Header timing check
Header timeout
Header ok
Stop if header ok
Wake up microcontroller
Start quietness check
360 ms watchdog
Enable data output
20 ms quietness check
Restart if signal detected
Switch demodulated signal to data output
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3.2 AGC Amplifier
Each of the three input stages contain an AGC amplifier to amplify the input signal from the Coil. The gain is adjusted by the automatic gain control circuit if a preamble signal is detected. The high dynamic range of the AGC amplifier enables the IC to work with input signals from 2.8 mVPP to 2.8VPP. After the AGC settling time has elapsed, the amplifier output delivers a 125-kHz signal with an amplitude adjusted for the following evaluation circuits (preamble detection, signal conditioner, wake-up).
3.3
Automatic Gain Control
For correct demodulation, the signal conditioner needs an appropriate internal signal amplitude. To control the input signal, the ATA5282 has a built-in digital AGC for each input channel. This gain control circuit regulates the internal signal amplitude to the reference level (Ref2, Figure 3-2 on page 6). The gain control uses the signal of the input channel with the highest amplitude for the regulation as well as signal for the signal conditioner. During the preamble, each period of the carrier signal decreases the gain if the internal signal exceeds the reference level. If the signal does not achieve the reference level, each period increases the gain. After 192 preamble periods, the standard gain control mode is activated. In this mode, the gain is decreased every two periods if the internal signal exceeds the reference level and increased every eight periods if the reference level is not achieved. These measures assure that the input signal's envelope deformation will be minimized. During the gaps between signal bursts, the gain control is frozen to avoid that the gain be modified by noise signals. The tuning range of the AGC is subdivided into 256 regulator steps. The settling time for the full tuning range requires 320 periods (192 + (2 x 64) periods) during a preamble phase. In standby listen mode, the gain is reset to the maximum value. A proper carrier signal activates the automatic gain control. The preamble (Figure 3-7 on page 10) with up to 320 periods of the 125 kHz magnetic field is used to control the gain of the input amplifiers. To detect the starting point of the header, the start gap should not exceed 256 s (32 periods of 125 kHz).
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Figure 3-2.
Automatic Gain Control
Transmitted signal
Coil input
Gain control reference Gap detection reference
Ref.2 100%
Gaincontrolled signal
Ref.1
50%
Demodulated output
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3.4 Field Strength RSSI (Received Signal Strength Indicator)
The digital value of the AGC counter is used as an indicator for the corresponding field strength of the input signal. The digital value can be accessed by the microcontroller via the serial interface.
Figure 3-3.
Field Strength as a Function of Coil Input Signal
255
Digital Value of Field Strength (RSSI_V)
224 192 max. 160 128 96 64 32 0 0,001 min.
Limiter active
0,01
0,1
1
10
Coil Input Signal (V CI ) PP
The characteristic gain control value versus the coil input signal (see Figure 3-3) can be calculated by using the following equation: RSSI_V = ROUND (32 x Ln(VCI)PP + 190) RSSI_V: Digital value of field strength Ln(): Natural logarithm function VCI: Coil input voltage With the variation of the gain the coil input impedance changes from high impedance to minimal 143 k (Figure 3-4). This impedance variation is an insignificant influence to the quality factor of the resonant circuits.
Figure 3-4.
Coil Input Impedance
10000 max. typ. min.
Z (k)
1000
100 1 10 100 1000 10000
Coil Input Signal (mVpp)
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3.5
Signal Conditioner
The signal conditioner operates on the demodulated output signal of all three channels.
Figure 3-5.
Function of Signal Conditioner
Medium signal strength
Internal signals
Input Channel 1 Internal GAP
High signal strength
Input Channel 2
Internal GAP Low signal strength Input Channel 3 Internal GAP Signal conditioner output (NDATA)
The AGC reduces the gain of all 3 channels with reference to the signal with the highest amplitude. This automatically reduces the gain of channels with medium or low input signal amplitudes which results in the suppression of further process of these channels. The logical combination of the 3 demodulated output signals mostly represents the signal with the highest input amplitude.
3.6
Preamble Detection
To prevent the circuit from unintended operations in a noisy environment, the preamble is checked to consist of 192 periods minimum. Three consecutive periods missing do not disturb counting. With this check passed, the circuit starts the internal oscillator at the end of the preamble (Figure 3-9 on page 12). The AGC needs a maximum of 256 steps for full range tuning of amplifiers.
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Before data transmission occurs the IC remains in standby listen mode. To prevent the circuit from unintended operations in a noisy environment, the preamble detection circuit checks the input signal. A valid signal is detected by a counter circuit after 192 carrier periods without interrupts. Short interrupts which are suppressed by the signal conditioner are tolerated. If a valid carrier (preamble) has been found, the circuit starts the automatic gain control. It requires up to 256 carrier periods for settling. The complete preamble should have at least 320 carrier periods.
3.7
Internal Oscillator
If the end of the preamble is detected, the internal oscillator starts operating. It works as a time base to generate the time windows for the header detection, the header time-out check, the 20-ms-no-signal check and the data transmission duration watchdog. An external resistor connected to TC selects the oscillators frequency and defines all internal timings.
3.8
Header Detection and Wake-up
The preamble needs to be followed by the specific header. This header ensures that the builtin header detection wakes up the controller only with a valid signal. One possible protocol used for wake-up and data transmission is shown in Figure 3-7 on page 10 and Figure 3-9 on page 12. The standard header information must be transferred in OOK-mode (On-Off-Keying) with a duty cycle of 50%. The header detection starts with the start gap. A valid header requires 8 consecutive samples of rising and falling edges before the NDATA pin switches from high to low.
Figure 3-6.
Standard Header
32 End of periods preamble of 125 kHz 16 periods of 125 kHz 16 16 periods periods off on
Standard header tOFF Demodulated internal signal Internal detection windows
tSTART_L tEND_L tSTART_S tEND_S tSTART_S tEND_S
1152 s tON
tSTART_S tEND_S
If no valid header has been detected within 2 ms, beginning at the end of the preamble, the header time-out check stops the oscillator and resets the gain control as well as the header detection circuit to their initial state. The circuit then waits for the next preamble.
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In case of corrupted data or in a noisy environment, the controller also may use the serial interface to reset the ATA5282 to the initial state. This is performed by shifting a specific command into the internal command register.
Figure 3-7.
Wake-up Protocol for 125-kHz ASK Modulation
Preamble
about 2.5 ms 320 periods of 125 kHz 32 periods off
Header
about 1 ms 16 16 periods periods on off
Synch
0.5 ms
Input signal Internally demodulated signal Header detection Internal wake-up NDATA/ NWAKEUP
Header valid
n Bit Data
End of Data
32 periods of 125 kHz
Input signal
Internal wake-up
0
NDATA/ NWAKEUP
1
1
20 ms no signal
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3.9 Data Output
The wake-up signal enables the data pin that delivers the received and demodulated data stream to the controller. Sampling and decoding has to be performed by the controller. An example for data coding is given in the "n Bit Data" field (Figure 3-7 on page 10). This kind of modulation requires an indication of the end of data, for example, by a burst that differs from the other transmitted bits. As the circuit does not check the received data (except the header), it is up to the base station which kind of modulation (pulse distance, Manchester, bi-phase...) is used. The data output signal is derived from the internal GAP detection. Table 3-1 describes how the timing depends on different conditions of the applied input signal. The Q-factor of the external LC-tank as well as the signal strength influence the pulse width of the output signal. Figure 3-8. Output Timing Conditions
100% 50% Coil input
Internal comporator output Internal NGAP
a b c d
a + b = Data delay time tON c + d = Data delay time tOFF
Table 3-1.
Input Signal
Typical Output Timing versus Signal Strength at 3.2V Supply Voltage
a, c (Figure 3-8) Depends on Q-factor b (Periods) no Q 3 to 5 3 to 5 3 to 5 Q 14 4 to 6 4 to 6 3 to 5 Q 20 5 to 7 5 to 7 3 to 5 no Q 3 to 5 3 to 5 3 to 5 d (Periods) Q 14 4 to 6 4 to 6 4 to 6 Q 20 4 to 6 4 to 6 4 to 6
Minimum, 2.8 mVPP Medium, VCI < 2.8VPP Strong, VCI 2.8VPP
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3.10
Current Profile and Reset Function
As long as the ATA5282 does not receive and recognize a valid preamble, it stays in a lowcurrent listen mode with the gain control and the header detection reset to their initial state. After the circuit has passed the preamble check, the internal oscillator and the watchdog (for a 360 ms interval) starts. This results in an increased current consumption. The target of the different reset sources is to reduce the current consumption as fast as possible back to the initial value. This can take place at the end of the header time-out check at the earliest. If no valid header has been detected within 2 ms, the circuit switches back to the initial state. With wake-up activated, three further mechanism are available to control the reset. One under control of the connected microcontroller, one if no signal is received and one unconditional after a fixed time. The controller may shift the SOFTRES-command into the internal command register to force the circuit into the reset state. This may be useful if the controller detects that the received data are corrupted. The ATA5282 itself permanently checks for incoming signals. An interval of 20 ms (no signal received) also leads to the reset state. If there is no valid signal within 20 ms, for example, in a noisy environment or due to customer protocol requirements, the watchdog forces the circuit into the reset state after a fixed time of 360 ms at the latest.
Figure 3-9.
Current Profile and Reset Timing
Preamble Start gap
Protocol Valid preamble detected Valid header detected Internal oscillator 2 ms interval
Header
n Bit Data
Header time out check
Reset if no header detected
20 ms interval
20 ms no data
reset if no data
360 ms interval
Data transmission duration watchdog
Unconditional reset
Current profile
4 A 2 A 2 A
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4. Serial Interface
4.1 General Description
The serial interface is an easy-to-handle 8-bit 2-wire interface. It always operates as a slave. The controller uses the NSCL input to shift a command into and data out of the internal shift register. The interface starts working with the first falling edge of NSCL. NDATA/NWAKEUP serves as bi-directional DATA I/O for command input and data output. The rising edge of NSCL is used to clock the command into the register of the ATA5282, while the falling edge is used to shift out the data. Data changes are always derived from the falling edge of NSCL. Two operating modes are implemented. One is the command mode that only requires an 8-bit input and does not prepare a data output. This mode is useful to control different operating modes of the ATA5282, as described on the following pages. The second mode is used to read out the current value of the AGC-counter that is related to the field strength of the input signal. The READ_FS command starts an internal sequence to store the value of the AGC into the shift register and switches the DATA I/O to output mode. After tACC, the controller must deliver another 8 shift clocks to clock out the information.
Figure 4-1.
Serial Interface
MSB
Command B C D E F G H
MSB
Data
DATA I/O (NDATA) NSCL
A
tSCL
tACC > 50 s
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4.2
Command and Data Register
The 8-bit command register is organized as follows:
Table 4-1.
MSB
Command Register
Command not used LSB TEST MOD 0 1 X X 0 1 0 1 0 0 1 1 0 1 0 1 No effect Reset circuit to initial state No effect Read AGC-counter (field strength) Coil input 1, 2, 3 active Select Coil input 1 (disable 2 and 3) Select Coil input 2 (disable 1 and 3) Select Coil input 3 (disable 1 and 2) Automatic Gain Control (AGC) active Function Default value after reset: 00 hex Application mode active Test mode active For future use For future use
FREEZE CH_SEL 1 CH_SEL 2 READ_FS SOFT_RES not used
0 1 Note:
AGC stopped with actual value These commands, except FREEZE- and READ_FS, cause a reset of AGC to initial state.
Table 4-2.
MSB
Data Register
Data LSB Function
AGC7 AGC6 AGC5 AGC4 AGC3 AGC2 AGC1 AGC0 Default value '00'hex Note: The content of the data register is updated every time a READ_FS command is given via the interface.
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4.3 Command Description
Note: Every command except FREEZE- and READ_FS causes a reset of the AGC to its initial state. Between every command should be a delay of 50 s.
4.3.1
TEST_MOD
Not for customer use, this mode is only used for production tests.
4.3.2 SOFT_RES
In addition to the internal hardware reset and watchdog functions, this bit allows the connected microcontroller to switch the circuit into the initial low-power state. All internal registers including the serial interface and the gain control counter are reset by this command.
4.3.3 READ_FS
As long as this bit is kept at 0, the interface is in write mode and accepts 8-bit commands only. Setting Read_FS to 1 enables to read out the digital 8-bit value of the gain control counter (RSSI), thus requiring two 8-bit accesses. The distance between the two accesses (tACC) must be > 50 s to allow proper operating and updating of the internal data register.
4.3.4 CH_SEL0,1
These two bits define the operation mode of the three channels. After reset, all channels are active. With the CH_SEL-bits, one of the three channels can be selected to be active, while the other two are disabled. The gain control is reset to the initial value if these bits are modified and operates only with the selected channel. This feature can be used for three-dimensional field strength measurements or to suppress the influence of noise from disturbing channels.
4.3.5 FREEZE
When set to 1, this bit disables the automatic gain control and maintains the actual value for the gain of the input amplifiers. Even when changing the input amplitudes (for example, modulation through noise or movement), the gain is kept constant.
4.3.6 Example
The example shows how to program the circuit to operate on channel 1 only and to measure the field strength of the Coil 1 input signal. Figure 4-2 shows the command entry which activates Coil 1 input only. The gain control counter is set to zero (highest sensitivity) by this command. The information is shifted into the ATA5282 with the rising edge of the shift clock.
Figure 4-2.
Select Coil Input 1
MSB Command DATA I/O (NDATA) NSCL
0
0
1
0
0
0
0
0
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Figure 4-3 shows the second step, the read-out of the actual field strength of the signal applied to Coil 1. When 128 steps have been passed, the gain control is finished and the value can be read out. This is performed by providing the command READ_FS with the information of the selected channel. 50 s later, the ATA5282 has updated and stored the information into the internal shift register. Now the microcontroller can read the actual information by generating the next 8 shift clock pulses. The information changes on the falling edge of the clock pulse.
Figure 4-3.
Read Field Strength of Channel 1
Read Command DATA I/O (NDATA) NSCL
MSB
Read field strength of coil 1 input signal 0 1 1 0 1 0 0
Field strength data internal operation
MSB
0
> 50 s Down-link Up-link
4.4
Reset Interface
To prevent the system from hanging or running into a deadlock condition due to disturbances on the NSCL line (hardware or software), a special function is provided to reset, the interface.
Figure 4-4.
Reset Interface
DATA I/O (NDATA) NSCL Reset interface
Setting the NSCL to a low level and generating 4 clock pulses at the NDATA pin resets all interface-relevant registers and flip-flops, thus cancelling the deadlock condition and resynchronizing the interface.
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5. Application
Figure 5-1 shows an application of the ATA5282. Combined with the antenna resonant circuit, the ATA5282 is used as wake-up receiver for the microcontroller. Additional to the antenna circuits the blocking filter - consisting of a RC element (R1 = 100, C1 = 4.7 F) - is necessary for the ATA5282. An additional resistor (R2 = 2 M/1%) should be placed at TC for oscillator tuning (optional: a parallel capacitor C2 with maximum 10 pF).
Figure 5-1.
Application Circuit
R1 C2
VDD
C1 R2 GND
125 kHz
X
TC
Timing
ATA5282
Central Board Controller
Antenna Driver ATA5278
Y
Header Detect
NDATA
Z
Serial Interace
NSCL
Microcontroller MARC4
UHF Receiver ATA5743
433 MHz
UHF Module ATA5757
Note:
Unused channels should be connected to VDD.
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Figure 5-2.
Pin Connection and Pin Protection
ATA5282
COIL1
1
Divider impedance 143 k to 5 M
8
VDD
VDD
COIL2
2
Divider impedance 143 k to 5 M 20 k 2 k
7
NDATA
VDD
COIL3
3
Divider impedance 143 k to 5 M 1 k
6
NSCL
VDD
VSS
4
18 k 1 k
5
TC
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6. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Power supply Input voltage (except coil inputs) Input current coil Input voltage coil ESD protection (human body) Operating temperature range Storage temperature range Soldering temperature Symbol VDD VIN ICI VCI VESD Tamb Tstg Tsld Value -0.3 to +6.5 VSS - 0.3 < VIN < VDD + 0.3 10 VDD - 3.5 < VCI < VDD + 3.5 4 -40 to +85 -40 to +130 260 Unit V V mA V kV C C C
7. Thermal Resistance
Parameters Thermal resistance junction-case Thermal resistance junction-ambient Symbol RthJC RthJA Value 260 240 Unit K/W K/W
8. Operating Range
Parameters Power supply range Operating temperature range Symbol VDD TOP Value 2 to 3.8 -40 to +85 Unit V C
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9. Electrical Characteristics
VSS = 0V, VDD = 0V to 3.8V, Tamb = -40C to 85C unless otherwise specified No. 1 1.1 1.2 1.3 1.4 1.5 1.6 Parameters Power supply Supply current (initial state, AGC off) Supply current (AGC active) Power on reset threshold Power up time Switch on VDD to circuit active 7 Test Conditions Pin 8 8 8 Symbol VDD IDD IDD VPOR VPON tRST 10 1 Min. 2 Typ. 3.2 2 4 1.5 Max. 3.8 4 6 1.9 100 100 Unit V A A V ms s Type* A A A A C C Power Supply and Coil Limiter
RESET reactivation caused by tBDN = 500 ns negative spikes on VDD Coil input voltage referred to VDD (Input Coil limiter for channels X, Y, Z) TC low current output Carrier frequency range Amplifiers Wake-up sensitivity Bandwidth Upper corner frequency Lower corner frequency 125-kHz input signal Without Coil Without Coil Without Coil Maximum/minimum value (decimal) of channels RSSI_Vmax - RSSI_Vmin (see Figure 3-3 on page 7) VIN 2.8 mVPP at 125 kHz VCI = 2.8 mVPP VCI = 2.8 VPP REXT = 2 M and CEXT maximum 10 pF VCI 1VPP Tolerance included oscillator tolerance ICI = 1 mA VDD = 2.0V VDD = 3.2V VDD = 3.8V VO_TC at 500 mV
1.71 1.72 1.73 1.8 1.9 2 2.1 2.2 2.3 2.4
1, 2, 3
VCI ITC fCF VSENS BW fu fo 205 100
1.2 1.4 1.55 250 280 150 2.8 150 180 30 4.9
VP VP VP nA kHz mVPP kHz kHz kHz
A
5 1, 2, 3 7
A D A C C C
2.5
Gain difference
1, 2, 3
GDIFF RIN CIN 143 10 60
16
A
2.6 2.7 2.8 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11
Input impedance Input capacitance Coils Input Range Digital Oscillator frequency Preamble periods Header detection windows (L = long, S = short) see Figure 3-6 on page 9 Shift clock period Data access time Data rate (Q < 20) Delay time RF signal to data Delay time RF signal to data
1, 2, 3 1, 2, 3 1, 2, 3
k pF dB
A C A
fOSC 1, 2, 3 nPAM tSTART_L tEND_L tSTART_S tEND_S 6 tNSCL tACC DRATE tON tOFF
80 320 160 315 40 200 10 50
90
100
kHz
A A
182 357 50 225
205 400 60 255
s s s s s s
D D A D C A A A A
125 kHz ASK 125 kHz ASK 125 kHz ASK
4 40 40
kbps s s
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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9. Electrical Characteristics (Continued)
VSS = 0V, VDD = 0V to 3.8V, Tamb = -40C to 85C unless otherwise specified No. 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Parameters Interface NSCL input level LOW NSCL input level HIGH NSCL input leakage current LOW NSCL input leakage current HIGH NDATA input level LOW NDATA input level HIGH NDATA input leakage current LOW NDATA input leakage current HIGH NDATA output level LOW NDATA output level HIGH VNSCL = VSS VNSCL = VDD VNSCL = VSS VNSCL = VSS VNDAT = VSS VNSCL = VSS VNDAT = VDD VNSCL = VSS INDAT = +70 A VNSCL = VDD INDAT = -70 A VNSCL = VDD 6 6 6 6 7 7 7 7 7 7 VIL_NSCL VIH_NSCL IIL_NSCL IIH_NSCL VIL_NDAT VIH_NDAT IIL_NDAT IIH_NDAT VOL_NDAT VOL_NDAT VSS 0.8 x VDD -200 0 VSS 0.8 x VDD -200 0 VSS 0.8x VDD 0.2 x VDD VDD 0 +200 0.2 x VDD VDD 0 +200 0.2 x VDD VDD V V nA nA V V nA nA V V A A A A A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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10. Ordering Information
Extended Type Number ATA5282-6AQH ATA5282-6APH Package TSSOP 8L TSSOP 8L Remarks 5000 pcs taped and reeled, Pb-free 500 pcs taped and reeled, Pb-free
11. Package Information
Figure 11-1. Package TSSOP 8L
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Atmel Corporation
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4694E-AUTO-08/05 xM

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